380 FFVkBuffer *ws_vk, uint32_t comp_offs[4], uint32_t comp_planes[4],
381 uint32_t ws_offset[4], uint32_t ws_stride[4],
382 uint32_t ws_count, uint32_t t, uint32_t nb_components)
388 { comp_offs[0], comp_offs[1], comp_offs[2], comp_offs[3] },
389 { comp_planes[0], comp_planes[1], comp_planes[2], comp_planes[3] },
390 { ws_offset[0], ws_offset[1], ws_offset[2], ws_offset[3] },
391 { ws_stride[0], ws_stride[1], ws_stride[2], ws_stride[3] },
402 VK_SHADER_STAGE_COMPUTE_BIT,
405 VkBufferMemoryBarrier2 buf_bar;
407 COMPUTE_SHADER_BIT, SHADER_STORAGE_READ_BIT,
408 SHADER_STORAGE_WRITE_BIT,
409 COMPUTE_SHADER_BIT, SHADER_STORAGE_READ_BIT, NONE_KHR,
411 vk->CmdPipelineBarrier2(exec->
buf, &(VkDependencyInfo) {
412 .sType = VK_STRUCTURE_TYPE_DEPENDENCY_INFO,
413 .pBufferMemoryBarriers = &buf_bar,
414 .bufferMemoryBarrierCount = 1,
418 vk->CmdDispatch(exec->
buf,
440 int plane_heights[4];
442 int offsets_dispatched = 0;
451 uint32_t ws_count = 0;
452 uint32_t ws_offset[4];
453 uint32_t ws_stride[4];
459 VkImageMemoryBarrier2 img_bar[8];
461 VkBufferMemoryBarrier2 buf_bar[2];
464 if (!
s->initialized) {
491 for (
int i = 0;
i <
desc->nb_components;
i++) {
494 plane_widths[
i] =
FFALIGN(plane_widths[
i],
s->shd_denoise.lg_size[0]);
495 plane_heights[
i] =
FFALIGN(plane_heights[
i],
s->shd_denoise.lg_size[1]);
498 comp_planes[
i] =
desc->comp[
i].plane;
500 ws_stride[
i] = plane_widths[
i];
501 ws_offset[
i] = ws_count;
502 ws_count += ws_stride[
i] * plane_heights[
i];
505 ws_size = ws_count *
sizeof(
float);
509 VK_BUFFER_USAGE_STORAGE_BUFFER_BIT |
510 VK_BUFFER_USAGE_SHADER_DEVICE_ADDRESS_BIT,
512 int_size *
s->opts.t *
desc->nb_components,
513 VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT));
515 VK_BUFFER_USAGE_STORAGE_BUFFER_BIT |
516 VK_BUFFER_USAGE_TRANSFER_DST_BIT,
518 ws_size *
s->
opts.t * 2,
519 VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT));
530 VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT,
531 VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT));
533 VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT,
534 VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT));
539 VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT,
540 VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
541 VK_ACCESS_SHADER_READ_BIT,
542 VK_IMAGE_LAYOUT_GENERAL,
543 VK_QUEUE_FAMILY_IGNORED);
548 VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT,
549 VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
550 VK_ACCESS_SHADER_WRITE_BIT,
551 VK_IMAGE_LAYOUT_GENERAL,
552 VK_QUEUE_FAMILY_IGNORED);
555 ALL_COMMANDS_BIT, NONE_KHR, NONE_KHR,
556 TRANSFER_BIT, TRANSFER_WRITE_BIT, NONE_KHR,
559 ALL_COMMANDS_BIT, NONE_KHR, NONE_KHR,
560 COMPUTE_SHADER_BIT, SHADER_STORAGE_READ_BIT, NONE_KHR,
562 vk->CmdPipelineBarrier2(exec->
buf, &(VkDependencyInfo) {
563 .sType = VK_STRUCTURE_TYPE_DEPENDENCY_INFO,
564 .pImageMemoryBarriers = img_bar,
565 .imageMemoryBarrierCount = nb_img_bar,
566 .pBufferMemoryBarriers = buf_bar,
567 .bufferMemoryBarrierCount = nb_buf_bar,
573 vk->CmdFillBuffer(exec->
buf, ws_vk->
buf, 0, ws_vk->
size, 0x0);
577 VK_IMAGE_LAYOUT_GENERAL, VK_NULL_HANDLE);
580 VK_IMAGE_LAYOUT_GENERAL, VK_NULL_HANDLE);
582 ws_vk, 0, ws_size *
s->
opts.t,
583 VK_FORMAT_UNDEFINED));
585 ws_vk, ws_size *
s->
opts.t, ws_size *
s->
opts.t,
586 VK_FORMAT_UNDEFINED));
590 VK_IMAGE_LAYOUT_GENERAL, VK_NULL_HANDLE);
592 VK_IMAGE_LAYOUT_GENERAL, VK_NULL_HANDLE);
594 ws_vk, 0, ws_size *
s->
opts.t,
595 VK_FORMAT_UNDEFINED));
597 ws_vk, ws_size *
s->
opts.t, ws_size *
s->
opts.t,
598 VK_FORMAT_UNDEFINED));
600 VkPipelineStageFlagBits2 ws_stage = VK_PIPELINE_STAGE_2_TRANSFER_BIT;
601 VkAccessFlagBits2 ws_access = VK_ACCESS_2_TRANSFER_WRITE_BIT;
603 int wg_invoc =
FFMIN((
s->nb_offsets - offsets_dispatched)/
TYPE_ELEMS,
s->opts.t);
605 { plane_widths[0], plane_widths[1], plane_widths[2], plane_widths[3] },
606 { plane_heights[0], plane_heights[1], plane_heights[2], plane_heights[3] },
607 {
s->strength[0],
s->strength[1],
s->strength[2],
s->strength[3], },
608 { comp_offs[0], comp_offs[1], comp_offs[2], comp_offs[3] },
609 { comp_planes[0], comp_planes[1], comp_planes[2], comp_planes[3] },
612 (uint64_t)int_stride,
619 COMPUTE_SHADER_BIT, SHADER_STORAGE_READ_BIT, NONE_KHR,
620 COMPUTE_SHADER_BIT, SHADER_STORAGE_WRITE_BIT, NONE_KHR,
622 vk->CmdPipelineBarrier2(exec->
buf, &(VkDependencyInfo) {
623 .sType = VK_STRUCTURE_TYPE_DEPENDENCY_INFO,
624 .pBufferMemoryBarriers = buf_bar,
625 .bufferMemoryBarrierCount = nb_buf_bar,
631 VK_SHADER_STAGE_COMPUTE_BIT,
633 vk->CmdDispatch(exec->
buf,
635 s->shd_vertical.lg_size[0],
641 COMPUTE_SHADER_BIT, SHADER_STORAGE_WRITE_BIT, NONE_KHR,
642 COMPUTE_SHADER_BIT, SHADER_STORAGE_READ_BIT,
643 SHADER_STORAGE_WRITE_BIT,
645 vk->CmdPipelineBarrier2(exec->
buf, &(VkDependencyInfo) {
646 .sType = VK_STRUCTURE_TYPE_DEPENDENCY_INFO,
647 .pBufferMemoryBarriers = buf_bar,
648 .bufferMemoryBarrierCount = nb_buf_bar,
654 VK_SHADER_STAGE_COMPUTE_BIT,
656 vk->CmdDispatch(exec->
buf,
658 s->shd_horizontal.lg_size[0],
664 COMPUTE_SHADER_BIT, SHADER_STORAGE_READ_BIT,
665 SHADER_STORAGE_WRITE_BIT,
666 COMPUTE_SHADER_BIT, SHADER_STORAGE_READ_BIT, NONE_KHR,
668 buf_bar[nb_buf_bar++] = (VkBufferMemoryBarrier2) {
669 .sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER_2,
670 .srcStageMask = ws_stage,
671 .dstStageMask = VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
672 .srcAccessMask = ws_access,
673 .dstAccessMask = VK_ACCESS_2_SHADER_STORAGE_READ_BIT |
674 VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT,
675 .srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
676 .dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
677 .buffer = ws_vk->
buf,
681 vk->CmdPipelineBarrier2(exec->
buf, &(VkDependencyInfo) {
682 .sType = VK_STRUCTURE_TYPE_DEPENDENCY_INFO,
683 .pBufferMemoryBarriers = buf_bar,
684 .bufferMemoryBarrierCount = nb_buf_bar,
687 ws_stage = buf_bar[1].dstStageMask;
688 ws_access = buf_bar[1].dstAccessMask;
691 { plane_widths[0], plane_widths[1], plane_widths[2], plane_widths[3] },
692 { plane_heights[0], plane_heights[1], plane_heights[2], plane_heights[3] },
693 { ws_offset[0], ws_offset[1], ws_offset[2], ws_offset[3] },
694 { ws_stride[0], ws_stride[1], ws_stride[2], ws_stride[3] },
695 {
s->patch[0],
s->patch[1],
s->patch[2],
s->patch[3] },
696 {
s->strength[0],
s->strength[1],
s->strength[2],
s->strength[3], },
697 { comp_offs[0], comp_offs[1], comp_offs[2], comp_offs[3] },
698 { comp_planes[0], comp_planes[1], comp_planes[2], comp_planes[3] },
701 (uint64_t)int_stride,
708 VK_SHADER_STAGE_COMPUTE_BIT,
709 0,
sizeof(wpd), &wpd);
710 vk->CmdDispatch(exec->
buf,
712 s->shd_weights.lg_size[0],
714 s->shd_weights.lg_size[1],
715 wg_invoc *
desc->nb_components);
718 }
while (offsets_dispatched < s->nb_offsets);
720 RET(
denoise_pass(
s, exec, ws_vk, comp_offs, comp_planes, ws_offset, ws_stride,
721 ws_count,
s->opts.t,
desc->nb_components));