29 #define REMATRIX_CHANNEL_FUNC(opt) \ 30 void ff_mlp_rematrix_channel_##opt(int32_t *samples, \ 31 const int32_t *coeffs, \ 32 const uint8_t *bypassed_lsbs, \ 33 const int8_t *noise_buffer, \ 35 unsigned int dest_ch, \ 37 unsigned int maxchan, \ 38 int matrix_noise_shift, \ 39 int access_unit_size_pow2, \ 45 #if HAVE_7REGS && HAVE_INLINE_ASM && HAVE_INLINE_ASM_NONLOCAL_LABELS 47 extern char ff_mlp_firorder_8;
48 extern char ff_mlp_firorder_7;
49 extern char ff_mlp_firorder_6;
50 extern char ff_mlp_firorder_5;
51 extern char ff_mlp_firorder_4;
52 extern char ff_mlp_firorder_3;
53 extern char ff_mlp_firorder_2;
54 extern char ff_mlp_firorder_1;
55 extern char ff_mlp_firorder_0;
57 extern char ff_mlp_iirorder_4;
58 extern char ff_mlp_iirorder_3;
59 extern char ff_mlp_iirorder_2;
60 extern char ff_mlp_iirorder_1;
61 extern char ff_mlp_iirorder_0;
63 static const void *
const firtable[9] = { &ff_mlp_firorder_0, &ff_mlp_firorder_1,
64 &ff_mlp_firorder_2, &ff_mlp_firorder_3,
65 &ff_mlp_firorder_4, &ff_mlp_firorder_5,
66 &ff_mlp_firorder_6, &ff_mlp_firorder_7,
68 static const void *
const iirtable[5] = { &ff_mlp_iirorder_0, &ff_mlp_iirorder_1,
69 &ff_mlp_iirorder_2, &ff_mlp_iirorder_3,
74 #define MLPMUL(label, offset, offs, offc) \ 75 LABEL_MANGLE(label)": \n\t" \ 76 "movslq "offset"+"offs"(%0), %%rax\n\t" \ 77 "movslq "offset"+"offc"(%1), %%rdx\n\t" \ 78 "imul %%rdx, %%rax\n\t" \ 79 "add %%rax, %%rsi\n\t" 81 #define FIRMULREG(label, offset, firc)\ 82 LABEL_MANGLE(label)": \n\t" \ 83 "movslq "#offset"(%0), %%rax\n\t" \ 84 "imul %"#firc", %%rax\n\t" \ 85 "add %%rax, %%rsi\n\t" 88 "xor %%rsi, %%rsi\n\t" 94 #define RESULT "%%rsi" 95 #define RESULT32 "%%esi" 99 #define MLPMUL(label, offset, offs, offc) \ 100 LABEL_MANGLE(label)": \n\t" \ 101 "mov "offset"+"offs"(%0), %%eax\n\t" \ 102 "imull "offset"+"offc"(%1) \n\t" \ 103 "add %%eax , %%esi\n\t" \ 104 "adc %%edx , %%ecx\n\t" 106 #define FIRMULREG(label, offset, firc) \ 107 MLPMUL(label, #offset, "0", "0") 109 #define CLEAR_ACCUM \ 110 "xor %%esi, %%esi\n\t" \ 111 "xor %%ecx, %%ecx\n\t" 113 #define SHIFT_ACCUM \ 114 "mov %%ecx, %%edx\n\t" \ 115 "mov %%esi, %%eax\n\t" \ 116 "movzbl %7 , %%ecx\n\t" \ 117 "shrd %%cl, %%edx, %%eax\n\t" \ 119 #define ACCUM "%%edx" 120 #define RESULT "%%eax" 121 #define RESULT32 "%%eax" 125 #define BINC AV_STRINGIFY(4* MAX_CHANNELS) 126 #define IOFFS AV_STRINGIFY(4*(MAX_FIR_ORDER + MAX_BLOCKSIZE)) 127 #define IOFFC AV_STRINGIFY(4* MAX_FIR_ORDER) 129 #define FIRMUL(label, offset) MLPMUL(label, #offset, "0", "0") 130 #define IIRMUL(label, offset) MLPMUL(label, #offset, IOFFS, IOFFC) 133 int firorder,
int iirorder,
135 int blocksize,
int32_t *sample_buffer)
137 const void *firjump = firtable[firorder];
138 const void *iirjump = iirtable[iirorder];
140 blocksize = -blocksize;
146 FIRMUL (ff_mlp_firorder_8, 0x1c )
147 FIRMUL (ff_mlp_firorder_7, 0x18 )
148 FIRMUL (ff_mlp_firorder_6, 0x14 )
149 FIRMUL (ff_mlp_firorder_5, 0x10 )
150 FIRMUL (ff_mlp_firorder_4, 0x0c )
151 FIRMUL (ff_mlp_firorder_3, 0x08 )
152 FIRMUL (ff_mlp_firorder_2, 0x04 )
153 FIRMULREG(ff_mlp_firorder_1, 0x00, 8)
156 IIRMUL (ff_mlp_iirorder_4, 0x0c )
157 IIRMUL (ff_mlp_iirorder_3, 0x08 )
158 IIRMUL (ff_mlp_iirorder_2, 0x04 )
159 IIRMUL (ff_mlp_iirorder_1, 0x00 )
162 "mov "RESULT
" ,"ACCUM" \n\t" 163 "add (%2) ,"RESULT
" \n\t" 164 "and %4 ,"RESULT
" \n\t" 166 "mov "RESULT32
", (%0) \n\t" 167 "mov "RESULT32
", (%2) \n\t" 168 "add $"BINC
" , %2 \n\t" 169 "sub "ACCUM" ,"RESULT
" \n\t" 170 "mov "RESULT32
","IOFFS
"(%0) \n\t" 178 :
"r"((
x86_reg)mask),
"r"(firjump),
179 "r"(iirjump) ,
"c"(filter_shift)
180 ,
"r"((int64_t)coeff[0])
181 :
"rax",
"rdx",
"rsi" 184 :
"m"(
mask),
"m"(firjump),
185 "m"(iirjump) ,
"m"(filter_shift)
186 :
"eax",
"edx",
"esi",
"ecx" 196 #if HAVE_7REGS && HAVE_INLINE_ASM && HAVE_INLINE_ASM_NONLOCAL_LABELS void(* mlp_rematrix_channel)(int32_t *samples, const int32_t *coeffs, const uint8_t *bypassed_lsbs, const int8_t *noise_buffer, int index, unsigned int dest_ch, uint16_t blockpos, unsigned int maxchan, int matrix_noise_shift, int access_unit_size_pow2, int32_t mask)
static atomic_int cpu_flags
Macro definitions for various function/variable attributes.
#define EXTERNAL_SSE4(flags)
Undefined Behavior In the C some operations are like signed integer dereferencing freed accessing outside allocated Undefined Behavior must not occur in a C it is not safe even if the output of undefined operations is unused The unsafety may seem nit picking but Optimizing compilers have in fact optimized code on the assumption that no undefined Behavior occurs Optimizing code based on wrong assumptions can and has in some cases lead to effects beyond the output of computations The signed integer overflow problem in speed critical code Code which is highly optimized and works with signed integers sometimes has the problem that often the output of the computation does not c
av_cold void ff_mlpdsp_init_x86(MLPDSPContext *c)
#define EXTERNAL_AVX2_FAST(flags)
#define INLINE_MMX(flags)
static const uint16_t mask[17]
void(* mlp_filter_channel)(int32_t *state, const int32_t *coeff, int firorder, int iirorder, unsigned int filter_shift, int32_t mask, int blocksize, int32_t *sample_buffer)
#define AV_CPU_FLAG_BMI2
Bit Manipulation Instruction Set 2.
#define REMATRIX_CHANNEL_FUNC(opt)
int av_get_cpu_flags(void)
Return the flags which specify extensions supported by the CPU.
__asm__(".macro parse_r var r\n\t""\\var = -1\n\t"_IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)".iflt \\var\n\t"".error \"Unable to parse register name \\r\"\n\t"".endif\n\t"".endm")
static const double coeff[2][5]