21#ifndef AVUTIL_RISCV_CPU_H
22#define AVUTIL_RISCV_CPU_H
48static inline av_const size_t ff_get_rv_vlenb(
void)
56 ".option pop\n" :
"=r" (vlenb));
64static inline av_const bool ff_rv_vlen_least(
unsigned int bits)
66#ifdef __riscv_v_min_vlen
67 if (
bits <= __riscv_v_min_vlen)
77 return bits <= (8 * ff_get_rv_vlenb());
__asm__(".macro parse_r var r\n\t" "\\var = -1\n\t" _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) ".iflt \\var\n\t" ".error \"Unable to parse register name \\r\"\n\t" ".endif\n\t" ".endm")
#define attribute_visibility_hidden
static const uint8_t bits[8]
static av_const bool ff_rv_zbb_support(void)
attribute_visibility_hidden bool ff_rv_zbb_supported